Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023
Public
Document Table of Contents

2.2. Timing Analysis Basic Concepts

This user guide introduces the following concepts to describe timing analysis:

Table 1.  Timing Analyzer Terminology
Term Definition
Arrival time The Timing Analyzer calculates the data and clock arrival time versus the required time at register pins.
Cell Device resource that contains look-up tables (LUT), registers, digital signal processing (DSP) blocks, memory blocks, or I/O elements. In Intel Stratix® series devices, the LUTs and registers are contained in logic elements (LE) modeled as cells.
Clock Named signal representing clock domains inside or outside of your design.
Clock-as-data analysis More accurate timing analysis for complex paths that includes any phase shift associated with a PLL for the clock path, and considers any related phase shift for the data path.
Clock hold time Minimum time interval that a signal must be stable on the input pin that feeds a data input or clock enable, after an active transition on the clock input.
Clock launch and latch edge The launch edge is the clock edge that sends data out of a register or other sequential element, and acts as a source for the data transfer. The latch edge is the active clock edge that captures data at the data port of a register or other sequential element, acting as a destination for the data transfer.
Clock pessimism Clock pessimism refers to use of the maximum (rather than minimum) delay variation associated with common clock paths during static timing analysis.
Clock setup time Minimum time interval between the assertion of a signal at a data input, and the assertion of a low-to-high transition on the clock input.
Maximum or minimum delay constraint A constraint that specifies timing path analysis with a non-default setup or hold relationship.
Net A collection of two or more interconnected components.
Node Represents a wire carrying a signal that travels between different logical components in the design. Most basic timing netlist unit. Used to represent ports, pins, and registers.
Pin Inputs or outputs of cells.
Port Top-level module inputs or outputs; for example, a device pin.
Metastability Metastability problems can occur when a signal transfers between circuitry in unrelated or asynchronous clock domains. The Timing Analyzer analyzes the potential for metastability in your design and can calculate the MTBF for synchronization register chains.
Multicorner analysis Timing analysis of slow and fast timing corners to verify your design under a variety of voltage, process, and temperature operating conditions.
Multicycle paths A data path that requires a non-default number of clock cycles for proper analysis.
Recovery and removal time Recovery time is the minimum length of time for the deassertion of an asynchronous control signal relative to the next clock edge. Removal time is the minimum length of time the deassertion of an asynchronous control signal must be stable after the active clock edge.
Timing netlist A Compiler-generated list of your design's synthesized nodes and connections. The Timing Analyzer requires this netlist to perform timing analysis.
Timing path The wire connection (net) between any two sequential design nodes, such as the output of a register to the input of another register.

Did you find the information on this page useful?

Characters remaining:

Feedback Message