Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023
Public

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3.6.5.3.1. Clock Divider Example (-divide_by)

A common form of generated clock is the divide-by-two register clock divider. The following example constraint creates a half-rate clock on the divide-by-two register.
create_clock -period 10ns -name clk_sys [get_ports clk_sys]
create_generated_clock -name clk_div_2 -divide_by 2 -source \
    [get_ports clk_sys] [get_pins reg|q]

To specify the clock pin of the register as the clock source:

create_clock -period 10ns -name clk_sys [get_ports clk_sys]
create_generated_clock -name clk_div_2 -divide_by 2 -source \
    [get_pins reg|clk] [get_pins reg|q]
Figure 99. Clock Divider
Figure 100.  Clock Divider Waveform

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