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2.2.1. Timing Path and Clock Analysis 2.2.2. Clock Setup Analysis 2.2.3. Clock Hold Analysis 2.2.4. Recovery and Removal Analysis 2.2.5. Multicycle Path Analysis 2.2.6. Metastability Analysis 2.2.7. Timing Pessimism 2.2.8. Clock-As-Data Analysis 2.2.9. Multicorner Timing Analysis 2.2.10. Time Borrowing
3.1. Timing Analysis Flow 3.2. Step 1: Specify Timing Analyzer Settings 3.3. Step 2: Specify Timing Constraints 3.4. Step 3: Run the Timing Analyzer 3.5. Step 4: Analyze Timing Reports 3.6. Applying Timing Constraints 3.7. Timing Analyzer Tcl Commands 3.8. Timing Analysis of Imported Compilation Results 3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 3.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
188.8.131.52. Report Fmax Summary 184.108.40.206. Report Timing 220.127.116.11. Report Timing By Source Files 18.104.22.168. Report Data Delay 22.214.171.124. Report Net Delay 126.96.36.199. Report Clocks and Clock Network 188.8.131.52. Report Clock Transfers 184.108.40.206. Report Metastability 220.127.116.11. Report CDC Viewer 18.104.22.168. Report Asynchronous CDC 22.214.171.124. Report Logic Depth 126.96.36.199. Report Neighbor Paths 188.8.131.52. Report Register Spread 184.108.40.206. Report Route Net of Interest 220.127.116.11. Report Retiming Restrictions 18.104.22.168. Report Register Statistics 22.214.171.124. Report Pipelining Information 126.96.36.199. Report Time Borrowing Data 188.8.131.52. Report Exceptions and Exceptions Reachability 184.108.40.206. Report Bottlenecks
3.6.1. Recommended Initial SDC Constraints 3.6.2. SDC File Precedence 3.6.3. Modifying Iterative Constraints 3.6.4. Using Entity-bound SDC Files 3.6.5. Creating Clocks and Clock Constraints 3.6.6. Creating I/O Constraints 3.6.7. Creating Delay and Skew Constraints 3.6.8. Creating Timing Exceptions 3.6.9. Using Fitter Overconstraints 3.6.10. Example Circuit and SDC File
220.127.116.11.1. Default Multicycle Analysis 18.104.22.168.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 22.214.171.124.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 126.96.36.199.4. Same Frequency Clocks with Destination Clock Offset 188.8.131.52.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 184.108.40.206.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 220.127.116.11.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 18.104.22.168.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
22.214.171.124. Timing Exception Precedence
If the same clock or node names occur in multiple timing exceptions, the Timing Analyzer observes the following order of timing exception precedence:
- Set False Path (set_false_path) is the first priority. False paths and clock groups have identical priority, except when you use the -latency_insensitive or -no_synchronizer options with a false path exception. With either option, the false path has priority over a clock group.
- Set Clock Groups (set_clock_groups) is the second priority.
- Set Minimum Delay (set_min_delay) and Set Maximum Delay (set_max_delay) are the third priority.
- Set Multicycle Path (set_multicycle_path) is the fourth priority.
The false path timing exception has the highest precedence. Within each category, assignments to individual nodes have precedence over assignments to clocks. For exceptions of the same type:
- -from <node> is the first priority.
- -to <node> is the second priority.
- -thru <node> is the third priority.
- -from <clock> is the fourth priority.
- -to <clock> is the fifth priority.
- set_max_delay 1 -from x -to y
- set_max_delay 2 -from x
- set_max_delay 3 -to y
The first exception has higher priority than either of the other two, since the first exception specifies a -from (while #3 doesn't) and specifies a -to (while #2 doesn't). In the absence of the first exception, the second exception has higher priority than the third, since the second exception specifies a -from, which the third does not. Finally, the remaining order of precedence for additional exceptions is order-dependent, such that the assignments most recently created overwrite, or partially overwrite, earlier assignments.
The set_net_delay, set_max_skew, and set_data_delay constraints analyze independently of minimum or maximum delays, or multicycle path constraints.
- The set_net_delay exception applies regardless of the existence of a set_false_path exception, or set_clock_groups exception, or other path-based constraint or exception. It is a net-based exception, and net-based and path-based exceptions are applied independently of each other.
- The set_max_skew exception applies on paths cut by an asynchronous clock group, and regardless of any set_false_path exception. Exclusive clock groups override max skew exceptions, because paths between exclusive clocks are entirely inactive and should not be analyzed for timing or skew requirements. This precedence allows you to define more targeted constraints on asynchronous CDC bus transfers.
- The set_data_delay exception specifies a maximum datapath delay exception for a given path. Exclusive clock groups override data delay exceptions, because paths between exclusive clocks are entirely inactive and should not be analyzed for timing or data delay requirements. Asynchronous clock groups do not override data delay exceptions. False path exceptions override data delay exceptions in the Intel Quartus Prime Pro software version 21.2 and earlier. Beginning in version 21.3, false path exceptions do not override data delay exceptions. This change in precedence allows you to write more targeted constraints on asynchronous CDC bus transfers.
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