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2.2.1. Timing Path and Clock Analysis 2.2.2. Clock Setup Analysis 2.2.3. Clock Hold Analysis 2.2.4. Recovery and Removal Analysis 2.2.5. Multicycle Path Analysis 2.2.6. Metastability Analysis 2.2.7. Timing Pessimism 2.2.8. Clock-As-Data Analysis 2.2.9. Multicorner Timing Analysis 2.2.10. Time Borrowing
3.1. Timing Analysis Flow 3.2. Step 1: Specify Timing Analyzer Settings 3.3. Step 2: Specify Timing Constraints 3.4. Step 3: Run the Timing Analyzer 3.5. Step 4: Analyze Timing Reports 3.6. Applying Timing Constraints 3.7. Timing Analyzer Tcl Commands 3.8. Timing Analysis of Imported Compilation Results 3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 3.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
126.96.36.199. Report Fmax Summary 188.8.131.52. Report Timing 184.108.40.206. Report Timing By Source Files 220.127.116.11. Report Data Delay 18.104.22.168. Report Net Delay 22.214.171.124. Report Clocks and Clock Network 126.96.36.199. Report Clock Transfers 188.8.131.52. Report Metastability 184.108.40.206. Report CDC Viewer 220.127.116.11. Report Asynchronous CDC 18.104.22.168. Report Logic Depth 22.214.171.124. Report Neighbor Paths 126.96.36.199. Report Register Spread 188.8.131.52. Report Route Net of Interest 184.108.40.206. Report Retiming Restrictions 220.127.116.11. Report Register Statistics 18.104.22.168. Report Pipelining Information 22.214.171.124. Report Time Borrowing Data 126.96.36.199. Report Exceptions and Exceptions Reachability 188.8.131.52. Report Bottlenecks
3.6.1. Recommended Initial SDC Constraints 3.6.2. SDC File Precedence 3.6.3. Modifying Iterative Constraints 3.6.4. Using Entity-bound SDC Files 3.6.5. Creating Clocks and Clock Constraints 3.6.6. Creating I/O Constraints 3.6.7. Creating Delay and Skew Constraints 3.6.8. Creating Timing Exceptions 3.6.9. Using Fitter Overconstraints 3.6.10. Example Circuit and SDC File
184.108.40.206.1. Default Multicycle Analysis 220.127.116.11.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 18.104.22.168.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 22.214.171.124.4. Same Frequency Clocks with Destination Clock Offset 126.96.36.199.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 188.8.131.52.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 184.108.40.206.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 220.127.116.11.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
18.104.22.168. Report CDC Viewer
The Timing Analyzer's Reports > Clock Domain Crossings > Report CDC Viewer... command allows you to configure and display a custom clock domain crossing report and the Clock Domain Crossing (CDC) Viewer. The CDC Viewer graphically displays the setup, hold, recovery, or removal analysis of all clock transfers in your design. The equivalent scripting command is report_cdc_viewer.
|Clocks||From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify.|
|Analysis type||Options are Setup, Hold, Recovery, or Removal. The Timing Analyzer reports the results for the type of analysis you select.|
|Transfers||Specifies the type of clock transfers to include or exclude from the report, including Timed transfers, Fully cut transfers, Clock groups, Inactive clocks, and Non-crossing transfers. You can specify the Maximum slack limit and Grid options for the report.|
|Detail level||Full shows all details of the report and Summary filters the details and shows summary data.|
|Report panel name||Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name, you can Overwrite or Append the file with latest data, and specify Grid or List format.
Note: In grid format reports, clocks with non-crossing transfers always appear if they have transfers between other clocks.
|Tcl command||Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file.|
You can specify the following options to customize CDC Viewer reporting:
|From Clock: and To Clock:||Filters the display according to the clock names you specify. Click From Clock: or To Clock: to search for specific clock names.|
|Legend||Defines the status colors. A color coded grid displays the clock transfer status. The clock headers list each clock with transfers in the design. The GUI truncates long clock names, but you can view the full name in a tool tip or by resizing the clock header cell. The GUI represents the generated clocks as children of the parent clock. A '+' icon next to a clock name indicates the presence of generated clocks. Clicking on the clock header displays the generated clocks associated with that clock.|
|Toggle Data||The text in each transfer cell contains data specific to each transfer. Turn on or off display of the following types of data:
|Show Filters and Show Legend||Turns on or off Filters and Legend.|
Figure 54. CDC Viewer Setup Transfers Report
Each block in the grid is a transfer cell. Each transfer cell uses color and text to display important details of the paths in the transfer. The color coding represents the following states:
|Cell Color||Color Legend|
|Black||Indicates no transfers. There are no paths crossing between the source and destination clock of this cell.|
|Green||Indicates passing timing. All timing paths in this transfer, that have not been cut, meet their timing requirements.|
|Red||Indicates failing timing. One or more of the timing paths in the transfer do not meet their timing requirements. If the transfer is between unrelated clocks, the paths likely require a synchronizer chain.|
|Blue||Indicates clock groups. The source and destination clocks of these transfers are cut by means of asynchronous clock groups.|
|Gray||Indicates a cut transfer. All paths in this transfer are cut by false paths. Therefore, timing analysis does not consider these paths.|
|Orange||Indicates inactive clocks. One of the clocks in the transfer is an inactive clock (with the set_active_clocks command). The Timing Analyzer ignores such transfers.|
Right-click menus allow you to perform operations on transfer cells and clock headers. When the operation is a Timing Analyzer report or SDC command, a dialog box opens containing the contents of the transfer cell.
|Copy||Copies the contents of the transfer cell or clock header to the clipboard.|
|Report Timing||Reports timing. Not available for transfer cells with no valid paths (gray or black cells).|
|Report Endpoints||Reports endpoints. Not available for transfer cells with no cut paths (gray or black cells).|
|Report False Path||Reports false paths. Not available for transfer cells with no valid paths (black cells).|
|Report Exceptions||Reports exceptions. Only available for clock group transfers (blue cells).|
|Report Exceptions (with clock groups)||Reports exceptions with clock groups. Only available for clock group transfers (blue cells).|
|Set False Path||Sets a false path constraint.|
|Set Multicycle Path||Sets a multicycle path exception.|
|Set Min Delay||Sets a min delay constraint.|
|Set Max Delay||Sets a max delay constraint.|
|Set Clock Uncertainty||Sets a clock uncertainty constraint.|
|Copy (include children)||Copies the name of the clock header, and the names of each of its derived clocks. This option only appears for clock headers with generated clocks.|
|Expand/Collapse All Rows/Columns||Shows or hides all derived clocks in the grid.|
|Create Slack Histogram||Generates a slack histogram report for the clock you select.|
|Report Timing From/To Clock||Generates a timing report for the clock you select. If you do not expand the clock to display derived clocks, the timing report includes all clocks that derive from the clock. To prevent this, expand the clock before right-clicking it.|
|Remove Clock(s)||Removes the clock you select from the design. If you do not expand the clock, timing analysis removes all clocks that derive from the clock.|
You can view CDC Viewer output in any of the following formats:
- A report panel in the Timing Analyzer
- Output in the Timing Analyzer Tcl console
- A plain-text file
- An HTML file you can view in a web browser.
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