Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023
Public

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3.5.1.16. Report Register Statistics

The Timing Analyzer's Reports > Design Metrics > Report Register Statistics command allows you to report the number of synchronous and asynchronous resets, hyper registers, and registers with clock enables in the design. You can use this information, combined with timing slack, congestion, and other analysis reports, to identify timing-critical parts of your design that can have resets removed or control schemes changed to meet timing requirements more efficiently.
Figure 71. Report Register Statistics
Note:
  • This report works similarly in both post-synthesis (DNI flow) and post-plan timing analysis. However, the report's Without a Clock column is more helpful for the post-synthesis timing analysis because conventional (non-SDC-on-RTL) SDCs are not typically loaded in the post-synthesis mode, so through this report, you can analyze how timing gets affected in the absence of the SDCs.
  • Clocks generated from derive_clocks commands do not count as user clocks.

The Without a Clock column informs you of the number of registers where no defined clock feeds the registers in the hierarchy shown in the Register Count column. A value of 0 in this column suggests that your design has SDC-defined clocks feeding registers in the design. The Unique Clocks column indicates the number of unique SDC-defined clocks feeding registers in the hierarchy identified by the Register Count. To view these columns, enable Show registers without clocks and Show the number of unique clocks feeding registers additional options in the dialog that displays when you run the report, as shown in the following image:

Figure 72. Report Register Statistics Additional Options Dialog