Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023

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Document Table of Contents Entity-bound Constraint Examples

The following examples show the automatic and manual scope of entity-bound constraints.
Figure 95. Automatic Scope Example

The following table illustrates the automatic scope of constraints as they apply to Automatic Scope Example.

Table 21.  Automatic Constraint Scoping Examples
Constraint Example Auto-Scope Constraint Interpretation for Instance X|Y
set_false_path -from [get_keepers a] set_false_path -from [get_keepers X|Y|a]
set_false_path -from [get_registers a] -to “*” set_false_path -from [get_registers X|Y|a]
set_false_path –from [get_clocks clk_1] –to [get_clocks clk_2] set_false_path –from [get_clocks clk_1] –to [get_clocks clk_2]
set_max_delay –from [get_ports in] -to [get_registers A] 2.0 set_max_delay –from [get_ports in] -to [get_registers X|Y|A] 2.0
get_ports *

get_ports *

get_clocks *

get_clocks *

get_ports a

get_ports a

get_clocks a

get_clocks a

Note: In table Automatic Scope Example, get_ports a and get_clocks a are simply examples that use an arbitrary name for the collection filter. These examples show that collection filters for get_ports and get_clocks are not subject to automatic constraint scoping because the ports and clocks are global, top-level objects that are never in the scope of an instance.
Figure 96. Manual Scope Example

The following table illustrates the manual scope of constraints as they apply to Manual Scope Example.

Table 22.  Manual Scope Constraint Examples
Constraint Example Manual Scope Constraint Interpretation
set_false_path –from [get_current_instance]|d\
     –to [get_current_instance]|e
set_false_path –from i1|inner|d –to i1|inner|e
set_false_path –from i2|inner|d –to i2|inner|e 
set_false_path –from i3|d –to i3|e
create_generated_clock –divide_by 2 –source \
     [get_ports inclk] –name \
     [get_current_instance]_divclk \
set_multicycle_path –from [get_current_instance]|a\
     –to [get_current_instance]|b 2
create_generated_clock –divide_by 2 –source \
     [get_ports inclk] –name “i1_divclk” i1|div
set_multicycle_path –from i1|a –to i1|b 2 \
create_generated_clock –divide_by 2 –source \
     [get_ports inclk] –name “i2_divclk” i2|div
set_multicycle_path –from i2|a –to i2|b 2

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