Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023
Public

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3.6.5.6.2. Clock Uncertainty

By default, the Timing Analyzer creates clocks that are ideal and have perfect edges. To mimic clock-level effects like jitter, you can add uncertainty to those clock edges. The Timing Analyzer automatically calculates appropriate setup and hold uncertainties and applies those uncertainties to all clock transfers in your design, even if you do not include the derive_clock_uncertainty command in your .sdc file. Setup and hold uncertainties are a critical part of constraining your design correctly.

The Timing Analyzer subtracts setup uncertainty from the data required time for each applicable path and adds the hold uncertainty to the data required time for each applicable path. This slightly reduces the setup and hold slack on each path.

The Timing Analyzer accounts for uncertainty clock effects for three types of clock-to-clock transfers: intraclock transfers, interclock transfers, and I/O interface clock transfers.

  • Intraclock transfers occur when the register-to-register transfer takes place in the device and the source and destination clocks come from the same PLL output pin or clock port.
  • Interclock transfers occur when a register-to-register transfer takes place in the core of the device and the source and destination clocks come from a different PLL output pin or clock port.
  • I/O interface clock transfers occur when data transfers from an I/O port to the core of the device or from the core of the device to the I/O port.

To manually specify clock uncertainty, use the set_clock_uncertainty command. You can specify the uncertainty separately for setup and hold. You can also specify separate values for rising and falling clock transitions. You can override the value that the derive_clock_uncertainty command automatically applies.

The derive_clock_uncertainty command accounts for PLL clock jitter, if the clock jitter on the input to a PLL is within the input jitter specification for PLL's in the target device. If the input clock jitter for the PLL exceeds the specification, add additional uncertainty to your PLL output clocks to account for excess jitter with the set_clock_uncertainty -add command. Refer to the device handbook for your device for jitter specifications.

You can also use set_clock_uncertainty -add to account for peak-to-peak jitter from a board when the jitter exceeds the jitter specification for that device. In this case you add uncertainty to both setup and hold equal to 1/2 the jitter value:

set_clock_uncertainty –setup –to <clock name>  \ 
    -setup –add <p2p jitter/2>
set_clock_uncertainty –hold –enable_same_physical_edge –to <clock name> \
    –add <p2p jitter/2>

There is a complex set of precedence rules for how the Timing Analyzer applies values from derive_clock_uncertainty and set_clock_uncertainty, which depend on the order of commands and options in your .sdc files. The Help topics below contain complete descriptions of these rules. These precedence rules are easier to implement if you follow these recommendations:

  • To assign your own clock uncertainty values to any clock transfers, put your set_clock_uncertainty exceptions after the derive_clock_uncertainty command in the .sdc file.
  • When you use the -add option for set_clock_uncertainty, the value you specify is additive to the derive_clock_uncertainty value. If you do not specify -add, the value you specify replaces the value from derive_clock_uncertainty.