Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023
Public

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3.6.8.5.1. Default Multicycle Analysis

By default, the Timing Analyzer performs a single-cycle analysis to determine the setup and hold checks. Also, by default, the Timing Analyzer sets the end multicycle setup assignment value to one and the end multicycle hold assignment value to zero.

The source and the destination timing waveform for the source register and destination register, respectively where HC1 and HC2 are hold checks 1 and 2 and SC is the setup check.

Figure 113. Default Timing DiagramThe timing waveforms show the source and destination registers of a data transfer. HC1 and HC2 are the hold checks that Timing Analyzer performs. SC is the setup check that Timing Analyzer performs.
Figure 114. Setup Check Calculation

The most restrictive default single-cycle setup relationship, with an implied end multicycle setup assignment of one, is 10 ns.

Figure 115. Default Setup Report
Figure 116. Hold Check CalculationThe figure shows the setup timing report with the launch and latch edge times highlighted.

The most restrictive default single-cycle hold relationship, with an implied end multicycle hold assignment of zero, is 0ns.

Figure 117.  Default Hold Report The figure shows the hold timing report with the launch and latch edge times highlighted.

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