Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023

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3.2. Step 1: Specify Timing Analyzer Settings

Before running timing analysis, you must open an Intel® Quartus® Prime project and run the Fitter to generate the timing netlist. You can consider and specify general settings for timing analysis, as well as other project-wide Compiler settings that impact the timing analysis results:
To specify general Timing Analyzer settings, follow these steps:
  1. Click File > New Project Wizard to create a new project, or click File > Open Project to open an existing project.
  2. Click Assignments > Settings > Timing Analyzer to open the Timing Analyzer settings.
    Figure 37. Timing Analyzer Page (Settings Dialog Box)

  3. In the Timing Analyzer page, specify one or more .sdc file for timing analysis, and any of the following options:
    Table 3.  Timing Analyzer General Settings
    Setting Description
    SDC files to include in the project Specifies the name and processing order of Synopsis Design Constraint (.sdc) files in the project.
    Interactive Timing Analysis Specify options for automatically running timing analysis, reading constraints, and generating reports automatically. Turn on or off:
    • Automatically launch Timing Analyzer GUI after a full compilation (default, on)
    • Automatically read constraints and update the timing netlist when project is opened in Timing Analyzer (default, on)
    • Automatically run setup summary report when project is opened in Timing Analyzer (default, on)
    Default Reporting Specify options to automatically Report worst-case paths during compilation (default, on). Specify the Paths reported per clock domain (default, 10), and whether to Show routing (default, off) in reports.
    Tcl Script Options Tcl Script File name specifies the file name for a custom timing analysis script. You can specify whether to Run default timing analysis before running custom script.
    Metastability Analysis Specifies how the Timing Analyzer identifies registers as being part of a synchronization register chain for metastability analysis.
  4. Consider and specify project-wide Compiler settings that can have a significant impact on Timing Analysis:
    Table 4.  Compiler Settings Impacting Timing Analysis
    Setting Description Location
    Enable multicorner support for Timing Analyzer and EDA Netlist Writer(default, on) Directs the Timing Analyzer to perform multicorner timing analysis by default, which analyzes the design against best-case and worst-case operating conditions. Assignments > Settings > Compilation Process Settings
    Optimization Mode (default, Balanced) Specifies the focus of Compiler optimization efforts during synthesis and fitting. Specify a Balanced strategy, or optimize for Performance, Area, Power, Routability, or Compile Time. Assignments > Settings > Compiler Settings
    SDC Constraint Protection (default, off)

    Verifies.sdc constraints in register merging. This option helps to maintain the validity of .sdc constraints through compilation.

    Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)
    Synchronization Register Chain Length (default, 3)

    Specifies the maximum number of registers in a row that the Compiler considers as a synchronization chain. The Compiler considers these registers for metastability analysis. The Compiler prevents optimizations of these registers, such as retiming. When gate-level retiming is enabled, the Compiler does not remove these registers.

    Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)
    Optimize Design for Metastability (default, on)

    This setting improves the reliability of the design by increasing its Mean Time Between Failures (MTBF). The Fitter increases the output setup slacks of synchronizer registers in the design. This slack can exponentially increase the design MTBF. This option only applies when using the Timing Analyzer for timing-driven compilation. Use the Timing Analyzer report_metastability command to review the synchronizers detected in your design and to produce MTBF estimates.

    Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)