Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer
ID
683243
Date
1/31/2023
Public
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2.2.1. Timing Path and Clock Analysis
2.2.2. Clock Setup Analysis
2.2.3. Clock Hold Analysis
2.2.4. Recovery and Removal Analysis
2.2.5. Multicycle Path Analysis
2.2.6. Metastability Analysis
2.2.7. Timing Pessimism
2.2.8. Clock-As-Data Analysis
2.2.9. Multicorner Timing Analysis
2.2.10. Time Borrowing
3.1. Timing Analysis Flow
3.2. Step 1: Specify Timing Analyzer Settings
3.3. Step 2: Specify Timing Constraints
3.4. Step 3: Run the Timing Analyzer
3.5. Step 4: Analyze Timing Reports
3.6. Applying Timing Constraints
3.7. Timing Analyzer Tcl Commands
3.8. Timing Analysis of Imported Compilation Results
3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History
3.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
3.5.1.1. Report Fmax Summary
3.5.1.2. Report Timing
3.5.1.3. Report Timing By Source Files
3.5.1.4. Report Data Delay
3.5.1.5. Report Net Delay
3.5.1.6. Report Clocks and Clock Network
3.5.1.7. Report Clock Transfers
3.5.1.8. Report Metastability
3.5.1.9. Report CDC Viewer
3.5.1.10. Report Asynchronous CDC
3.5.1.11. Report Logic Depth
3.5.1.12. Report Neighbor Paths
3.5.1.13. Report Register Spread
3.5.1.14. Report Route Net of Interest
3.5.1.15. Report Retiming Restrictions
3.5.1.16. Report Register Statistics
3.5.1.17. Report Pipelining Information
3.5.1.18. Report Time Borrowing Data
3.5.1.19. Report Exceptions and Exceptions Reachability
3.5.1.20. Report Bottlenecks
3.6.1. Recommended Initial SDC Constraints
3.6.2. SDC File Precedence
3.6.3. Modifying Iterative Constraints
3.6.4. Using Entity-bound SDC Files
3.6.5. Creating Clocks and Clock Constraints
3.6.6. Creating I/O Constraints
3.6.7. Creating Delay and Skew Constraints
3.6.8. Creating Timing Exceptions
3.6.9. Using Fitter Overconstraints
3.6.10. Example Circuit and SDC File
3.6.5.1. Creating Base Clocks
3.6.5.2. Creating Virtual Clocks
I/O Constraints with Virtual Clocks
Virtual Clock Constraints
3.6.5.3. Creating Generated Clocks (create_generated_clock)
3.6.5.4. Deriving PLL Clocks
3.6.5.5. Creating Clock Groups (set_clock_groups)
3.6.5.6. Accounting for Clock Effect Characteristics
3.6.5.7. Constraining CDC Paths
3.6.8.5.1. Default Multicycle Analysis
3.6.8.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
3.6.8.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
3.6.8.5.4. Same Frequency Clocks with Destination Clock Offset
3.6.8.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
3.6.8.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
3.6.8.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
3.6.8.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
3.6.5.2. Creating Virtual Clocks
A virtual clock is a clock without a real source in the design, or a clock that does not interact directly with the design. You can use virtual clocks in I/O constraints to represent clocks that drive external devices connected to the FPGA..
To create virtual clocks, use the create_clock constraint with no value for the <targets> option.
This following example defines a 100 MHz virtual clock because the command includes no <targets>.
create_clock -period 10 -name my_virt_clk
I/O Constraints with Virtual Clocks
You can use a base clock to constrain the circuit in the FPGA and a virtual clock to represent the clock driving the external device. .
Figure 97. Virtual Clock Board TopologyThe figure shows the base clock (system_clk), virtual clock (virt_clk), and output delay for the virtual clock constraints example
The following example creates the 10 ns virt_clk virtual clock, with a 50% duty cycle, with the first rising edge occurring at 0 ns. The virtual clock can then become the clock source for an output delay constraint.
Virtual Clock Constraints
#create base clock for the design
create_clock -period 5 [get_ports system_clk]
#create the virtual clock for the external register
create_clock -period 10 -name virt_clk
#set the output delay referencing the virtual clock
set_output_delay -clock virt_clk -max 1.5 [get_ports dataout]
set_output_delay -clock virt_clk -min 0.0 [get_ports dataout]