High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

ID 683189
Date 3/29/2024
Document Table of Contents

6.6. Soft AXI Switch

Beginning with the Quartus® Prime software version 20.1, the HBM2 IP supports a soft 4x4 AXI switch that provides each AXI master the ability to access the memory space of its corresponding two HBM2 Channels or four HBM2 Pseudo Channels (one HBM2 Channel = two HBM2 Pseudo Channels) in the HBM2 DRAM.

The following figure shows the switch implementation when enabled for HBM2 Channels 0 and 1, through the HBM2 IP GUI. Four AXI Switches can be implemented per HBM2 interface.

Figure 32. 4×4 HBM2 AXI Switch