High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

ID 683189
Date 3/29/2024
Document Table of Contents

5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP

This section describes how to simulate the generated HBM2 IP.

Simulation Assumptions

The parameter settings that you make on the Controller tab affect efficiency during simulation. In the default configuration, with the default parameter settings, the traffic generator issues sequential transactions.

Supported Simulators

The HMB2 IP supports the following simulators:

  • ModelSim SE
  • Questa* Advanced Simulator
  • Questa*-Intel FPGA Edition
  • Aldec Riviera-PRO*
  • Synopsys* VCS
  • Xcelium* Parallel Simulator