High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

ID 683189
Date 3/29/2024
Document Table of Contents

2.1. HBM2 in Intel® Stratix® 10 Devices

Stratix® 10 devices incorporate a high-performance FPGA fabric along with a HBM2 DRAM in a single package. Stratix® 10 devices support up to a maximum of two HBM2 interfaces.

Stratix® 10 devices incorporate Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to implement a silicon bridge between HBM2 DRAM memory and the Universal Interface Block Subsystem (UIBSS), which contains the HBM2 controller (HBMC), physical-layer interface (PHY), and I/O ports to interface to the HBM2 stack.

As illustrated below, each Stratix® 10 device contains a single universal interface bus per HBM2 interface, supporting 8 independent channels.

The user interface to the HBM2 controller is maintained through the AXI4 protocol. Sixteen AXI interfaces are available in the user interface from each HBM2 controller, with one AXI interface available per HBM2 Pseudo Channel. HBM2 DRAM density of 4GB and 8GB are supported.

Figure 1.  Stratix® 10 Device with UIB, EMIB, and HBM2 DRAM