High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

ID 683189
Date 3/29/2024
Document Table of Contents

7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing

The maximum HBM2 memory interface frequency is based on the Stratix® 10 device speed grade. The maximum core interface frequency is limited by the frequency at which the core logic can meet timing.

For the best HBM2 efficiency, ensure that your user logic follows best design practices. Take care to avoid combinatorial paths between the AXI master and slave input and output signals. Add pipeline registers as necessary and reduce logic levels in timing-critical paths to successfully meet core timing requirements. The Backpressure Latency feature allows you to add up to two register stages between the user interface and the HBM2 IP. Refer to Improving User Logic to HBM2 Controller AXI Interface Timing for details on Backpressure Latency.

The following documents provide detailed information on the Stratix® 10 device architecture and design techniques that you can adopt to achieve the best core performance:

  • The Stratix® 10 High Performance Design Handbook.
  • The Timing Closure and Optimizations chapter of the Design Optimization User Guide: Quartus® Prime Pro Edition .