High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

ID 683189
Date 3/29/2024
Document Table of Contents

5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator

  1. Navigate to: project_directory>/sim/ed_sim/xcelium.
  2. Type sh xcelium_setup.sh to launch the Xcelium simulator.
  3. To view the simulation results, write the output to a log file. The simulation log provides efficiency data and other useful information.