High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

ID 683189
Date 3/29/2024
Document Table of Contents

6.5.6. User Interrupt

An interrupt signal occurs when one or more of the Error Status signals are TRUE. You can configure the conditions that help to trigger the interrupt signal.

The various status signals on which you can generate the interrupt include the following:

  • Single-bit error (SBE) or double-bit error (DBE) of AXI Read Data or internal RAM used for Write and Read data storage
  • Read Data parity error (RDPE) or Write Data parity error (WDPE) of AXI Read Data
  • Address Command parity error
  • Calibration