High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

ID 683189
Date 3/29/2024
Document Table of Contents Interrupt Status

You can read the interrupt status from address 16’h0102 for Pseudo Channel 0 and 16’h0202 for Pseudo Channel 1. The interrupt signal is cleared when the individual error status signals that contribute to the interrupt are cleared and the corresponding error counters are cleared.
Table 40.  Read Data Definition for Interrupt Status
Read Data Bit Definition Description
[0] Interrupt asserted when one of the following events occurs:
  • Single-bit error
  • Double-bit error
  • Read Data parity error
  • Write Data parity error
  • Address Command parity error
  • CATTRIP assertion
  • Calibration status failure
[15:1] Reserved.