50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Public
Document Table of Contents

6.3. Transceivers

The transceivers require a separately instantiated advanced transmit (ATX) PLL to generate the high speed serial clock. For the 50GbE IP core, you can use the same ATX PLL for both transceivers. In comparison to the fractional PLL (fPLL) and clock multiplier unit PLL, the ATX PLL has the best jitter performance and supports the highest frequency operation.
Table 13.   Transceiver Signals

Signal

Direction

Description

tx_serial[1:0] Output TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial[1:0] Input RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref Input The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 644.53125 MHz.
tx_serial_clk[1:0] Input High speed serial clock driven by the ATX PLL. The frequency of this clock is 12.890625 GHz.
tx_pll_locked Input Lock signal from ATX PLL. Indicates all ATX PLL(s) are locked.

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