50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Public
Document Table of Contents

2.5.2. Adding the Transceiver PLL

The 50GbE IP core targets Arria® 10 GT devices. Arria® 10 GT devices require an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware.

Figure 5. PLL Configuration ExampleThe TX transceiver PLL is instantiated with an ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the 50GbE IP core.

You can use the IP Catalog to create a transceiver PLL.

  • Select Arria 10 Transceiver ATX PLL.
  • In the parameter editor, set the following parameter values:
    • PLL output frequency to 12890.625 MHz. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 25.78125 Gbps data rate through the transceiver.
    • PLL reference clock frequency to 644.53125 MHz.

You must connect the ATX PLL to the 50GbE IP core as follows:

  • Connect the clock output port of the ATX PLL to the tx_serial_clk input pin for each 50GbE IP core PHY link to the same output port of the ATX PLL. Connect the ATX PLL output port to both tx_serial_clk[1] and tx_serial_clk[0].
  • Connect the pll_locked output port of the ATX PLL to the tx_pll_locked input port of the 50GbE IP core.
  • Drive the ATX PLL reference clock port and the 50GbE IP core clk_ref input port with the same clock. The clock frequency must be the frequency you specify for the ATX PLL IP core PLL reference clock frequency parameter.

Did you find the information on this page useful?

Characters remaining:

Feedback Message