50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Public
Document Table of Contents

6.2. RX MAC Interface to User Logic

The RX MAC provides an Avalon-ST interface to the FPGA fabric. The datapath comprises 2, 64-bit words.
Table 12.   Avalon-ST RX Datapath All interface signals are clocked by the clk_rxmac clock.

Signal

Direction

Description

clk_rxmac Output Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when rx_pcs_ready is asserted. The frequency of this clock is 390.625 MHz. All RX MAC interface signals are synchronous to clk_rxmac.
l2_rx_data[127:0] Output

Data output from the MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard.

l2_rx_preamble[63:0] Output

Received preamble data. Available when you select PREAMBLE PASS-THROUGH mode.

Valid when l2_rx_startofpacket is asserted.
l2_rx_valid Output When asserted, indicates that l2_rx_data[127:0] is driving data. The IP core need not assert this signal continuously between the assertions of l2_tx_startofpacket and l2_tx_endofpacket for the same packet. During alignment marker cycles, the IP core drives IDLE cycles.
l2_rx_startofpacket Output

When asserted, indicates the first byte of a frame.

In PREAMBLE PASS-THROUGH mode, marks the first byte of the preamble.

l2_rx_endofpacket Output When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position.
l2_rx_empty[3:0] Output Specifies the number of empty bytes when l2_rx_endofpacket is asserted.

The packet can end at any byte position. The empty bytes are the low-order bytes.

l2_rx_error[5:0] Output

When asserted in the same cycle as l2_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l2_rx_error specify the following errors:

  • l2_rx_error[5]: Unused.
  • l2_rx_error[4]: Payload length error. If the length field is <1535 bytes, the received payload length is less than what is advertised in payload length field.
  • l2_rx_error[3]: Oversized frame. The frame size is greater than the value specified in the RXMAC_SIZE_CONFIG register.
  • l2_rx_error[2]: Undersized frame – The frame size is less than 64 bytes. Frame size = header size + payload size.
  • l2_rx_error[1]: CRC Error. The computed CRC value differs from the received CRC.
  • l2_rx_error[0]: Malformed packet. The packet is terminated with a non-terminate control character. When this bit is asserted, l2_rx_error[1] is also asserted.
l2_rxstatus_valid Output When asserted, indicates that l2_rxstatus_data is driving valid data.
l2_rxstatus_data[39:0] Output

Specifies information about the received frame. The following fields are defined:

  • [Bit 39]: When asserted, indicates a PFC frame
  • [Bit 38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
Figure 19.  50GbE MAC to Client Avalon-ST Interface l2_rx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l2_rx_data[127:120] , 0xabe42339 . . . in this timing diagram..

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