50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Document Table of Contents

2.2. Specifying the 50GbE Core Parameters and Options

The 50GbE parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Intel® Quartus® Prime software.
  1. Depending on whether you are using the Intel® Quartus® Prime Pro Edition software or the Intel® Quartus® Prime Standard Edition software, perform one of the following actions:
    • In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
    • In the Intel® Quartus® Prime Standard Edition software, in the IP Catalog (Tools > IP Catalog), select the Arria 10 target device family.
  2. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The New IP Variation window appears.
  3. In the New IP Variation dialog box, specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .qsys (in Intel® Quartus® Prime Standard Edition) or <your_ip> .ip (in Intel® Quartus® Prime Pro Edition).
  4. In the Intel® Quartus® Prime Standard Edition software, you must select a specific Intel® Arria® 10 device in the Device field, or keep the default device the Quartus Prime software proposes.
  5. Click OK. The parameter editor appears.
  6. On the IP tab, specify the parameters for your IP core variation. Refer to 50GbE Parameters for information about specific IP core parameters.
  7. Optionally, to generate a simulation testbench or compilation and hardware design example, follow the instructions in the Intel® Arria® 10 50G Ethernet Design Example User Guide.
  8. Click Generate HDL. The Generation dialog box appears.
  9. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
    Note: A functional VHDL IP core is not available. Specify Verilog HDL only, for your IP core variation.
  10. Click Finish. The parameter editor adds the top-level .qsys or .ip file to the current project automatically. If you are prompted to manually add the .qsys or .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  11. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.