50 Gbps Ethernet IP Core User Guide

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ID 683158
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the 50GbE Core 2. Getting Started 3. 50GbE Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control and Status Register Descriptions 8. Debugging the Link 9. Document Revision History
1. About the 50GbE Core x
1.1. 50GbE Supported Features 1.2. 50GbE Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization
1.2. 50GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 50GbE Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50GbE Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Intel® Arria® 10 Devices 2.5.4. Placement Settings for the 50GbE Core
4. Functional Description x
4.1. 50GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 50GbE Core Functional Description x
4.1.1. 50GbE Core TX MAC Datapath 4.1.2. 50GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. 50 GbE RX PCS
4.1.1. 50GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion
4.1.2. 50GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. IP Core Malformed Packet Handling 4.1.2.4. Length/Type Field Processing 4.1.2.5. RX CRC Checking and Dynamic Forwarding
4.1.2.4. Length/Type Field Processing x
4.1.2.4.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals
7. Control and Status Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers
1. About the 50GbE Core
2. Getting Started
3. 50GbE Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control and Status Register Descriptions
8. Debugging the Link
9. Document Revision History

4.2.1. Order of Transmission

The IP core transmits bytes on the Ethernet link starting with the preamble and ending with the FCS in accordance with the IEEE 802.3 standard. On the transmit client interface, the IP core expects the client to send the most significant bytes of the frame first, and to send each byte in big-endian format. Similarly, on the receive client interface, the IP core sends the client the most significant bytes of the frame first, and orders each byte in big-endian format.

Figure 15. Byte Order on the Client Interface LanesDescribes the byte order on the Avalon® streaming interface. Destination Address[40] is the broadcast/multicast bit (a type bit), and Destination Address[41] is a locally administered address bit.


For example, the destination MAC address includes the following six octets AC-DE-48-00-00-80. The first octet transmitted (octet 0 of the MAC address described in the 802.3 standard) is AC and the last octet transmitted (octet 5 of the MAC address) is 80. The first bit transmitted is the low-order bit of AC, a zero. The last bit transmitted is the high order bit of 80, a one.

The preceding table and the following figure show that in this example, 0xAC is driven on DA5 (DA[47:40]) and 0x80 is driven on DA0 (DA[7:0]).

Figure 16. Octet Transmission on the 50GbE Avalon® Streaming Interface In the following diagram Preamble pass through is disabled.
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