50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Document Table of Contents

2.4. Generated File Structure

The Quartus Prime software generates the following IP core output file structure.

For information about the file structure of the design example, refer to the Arria 10 50GbE Design Example User Guide.

Figure 4. IP Core Generated Files
Table 7.  IP Core Generated Files

File Name


<your_ip>.qsys ( Quartus® Prime Standard Edition only)

The Qsys system or top-level IP variation file. <your_ip> is the name that you give your IP variation.

<your_ip>.ip ( Quartus® Prime Pro Edition only)


Describes the connections and IP component parameterizations in your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Intel® Nios® II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios® II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.

This IP core does not support VHDL. However, the Quartus® Prime software generates this file.


A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<your_ip>_generation.rpt IP or Qsys generation log file. A summary of the messages during IP generation.
<your_ip>.debuginfo Contains post-generation information. Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect. ( Quartus® Prime Standard Edition only)
<your_ip>.qgsimc Lists simulation parameters to support incremental regeneration. ( Quartus® Prime Pro Edition only)
<your_ip>.qgsynthc Lists synthesis parameters to support incremental regeneration. ( Quartus® Prime Pro Edition only)

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus Prime software.

<your_ip>.csv Contains information about the upgrade status of the IP component.


A Block Symbol File (.bsf) representation of the IP variation for use in Quartus Prime Block Diagram Files (.bdf).


Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<your_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<your_ip>.sip Contains information required for NativeLink simulation of IP components. You must add the .sip file to your Quartus Prime project. ( Quartus® Prime Standard Edition only)
<your_ip>_inst.v and _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.

This IP core does not support VHDL. However, the Quartus® Prime software generates the _inst.vhd file.

<your_ip>.regmap If IP contains register information, .regmap file generates. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in the System Console.

Allows hard processor system (HPS) System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name.



HDL files that instantiate each submodule or child IP core for synthesis or simulation.

This IP core does not support VHDL. However, the Quartus® Prime software generates this file.


Contains a ModelSim script msim_setup.tcl to set up and run a simulation.


Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.



Contains a shell script vcs_setup.sh to set up and run a VCS® simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX® simulation.


Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

submodules/ Contains HDL files for the IP core submodule.
<child IP cores>/ For each generated child IP core directory, Qsys generates synth/ andsim/ sub-directories.

Did you find the information on this page useful?

Characters remaining:

Feedback Message