50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Public
Document Table of Contents
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1. About the 50GbE Core

Updated for:
Intel® Quartus® Prime Design Suite 17.0

The 50GbE core implements the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50GbE core is a 64-bit Avalon® streaming interface. It maps to one 25.78125 Gbps transceiver. The IP core optionally includes the IEEE 802.3-2018 Clause 108 Reed-Solomon forward error correction (RS-FEC) for support of IEEE802.3-2018 Clause 107 25GBASE-R PCS. IEEE 802.3 Clause 73 Auto-Negotiation and IEEE 802.3 Clause 74 CR/KR-FEC are not supported. Transceiver interface to 25GBASE-SR optical Physical Medium Dependent (PMD) transceiver is supported.

The Intel®  50G Ethernet IP core implements the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50G Ethernet IP core is a 128-bit Avalon® Streaming (Avalon-ST) interface. It maps to two 25.78125 Gbps transceivers.

The IP core provides standard media access control (MAC) and physical coding sublayer (PCS), and PMA functions shown in the following block diagram. The PHY comprises the PCS and PMA.

Figure 1.  50GbE MAC and PHY IP Clock Diagram

The following block diagram shows an example of a network application with 50GbE MAC and PHY.

Figure 2. Example Network Application