50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Document Table of Contents

9. Document Revision History

Date Quartus Prime Version Changes
2017.11.09 17.0

Added link to KDB Answer that provides workaround for potential jitter on Intel® Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Handling Potential Jitter in Intel Arria 10 Devices and to Compiling the Full Design and Programming the FPGA .

Reorganized Features list for reading clarity. Refer to 50GbE Supported Features.

Clarified that both read and write accesses to undefined registers or register fields, including accesses to registers and register fields not defined in the current IP core variation, return unspecified results. Refer to Control and Status Register Descriptions.

Clarified that the reset_status signal remains visible in future releases for backward compatiblity, rather than being removed. The design must tie this input signal low. Refer to Avalon Memory-Mapped Management Interface.

2017.05.08 17.0 Initial public release.

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