50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Public
Document Table of Contents

1.1. 50GbE IP Core Supported Features

The 50GbE IP core supports the following features:

  • Parameterizable through the IP Catalog available with the Quartus® Prime software.
  • Designed to the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and designed to the IEEE 802.3by 25Gb Ethernet draft specification.
  • Designed to the IEEE 802.3ba-2012 High Speed Ethernet Standard available on the IEEE website (www.ieee.org).
  • Soft PCS logic that interfaces seamlessly to Intel® FPGA 25.78125 gigabits per second (Gbps) serial transceivers.
  • Avalon® Memory-Mapped ( Avalon® -MM) management interface to access the IP core control and status registers.
  • Avalon® Streaming ( Avalon® -ST) data path interface connects to client logic.
  • Support for jumbo packets, defined as packets greater than 1500 bytes.
  • Receive (RX) CRC removal and pass-through control.
  • Transmit (TX) CRC generation.
  • RX CRC checking and error reporting.
  • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
  • Optional RX strict SFD checking per IEEE specification.
  • RX malformed packet checking per IEEE specification.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard
  • Hardware and software reset control.
  • MAC provides RX cut-through frame processing; MAC does not support RX store-and-forward capability.
  • Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
  • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
  • Optional access to Altera Debug Master Endpoint (ADME) for serial link debugging.
  • Ready latency of 0 clock cycles for Avalon-ST TX interface.

For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet Standard.

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