126.96.36.199. Transmitter Transport Layer
To verify the data integrity of the data stream through the transmitter (TX) JESD204C Intel® FPGA IP and transport layer, the DAC JESD core is configured to check the PRBS test pattern that is transmitted from the test pattern generator of the FPGA. PRBS pattern checker is used to check the data integrity of DAC transport layer.
|Test Case||Objective||Description||Passing Criteria|
|TXTL.1||Check the transport layer mapping of the data channel using PRBS test pattern.||
The following signals in <ip_variant_name>_base.v are tapped:
The txframe_clk is used as the sampling clock for the Signal Tap.
Check the following in the DAC:
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