AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
Public
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1.3.1.1. Receiver Data Link Layer

This test area covers the test cases for sync header alignment (SHA) and extended multiblock alignment (EMBA).

The JESD204C RX IP will start link operation after rx_rst_n is deasserted. In a typical user application, all run-time registers should be configured when the Avalon® memory-mapped configuration space is out of reset, and before the link and transport layers are out of reset. Upon rx_rst_n deassertion, the JESD204C RX IP will perform SHA and EMB alignment.

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