1.4.3. DAC Test Results
The following table shows the results for test cases TXRST.1 and TXTL.1 with subclass 0 and FCLK_MULP = 2.
|Test No.||L||M||F||E||Lane Rate (Mbps)||DAC Rate (Msps)||Link Clock (MHz)||Result|
The following figure shows the Signal Tap waveform of the PRBS pattern data transmitted to FPGA transmitter transport layer.
The following figure shows the result of the pattern checker at output data of DAC transport layer.
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