AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.3.1.1.2. Extended Multiblock Alignment (EMBA)

Table 2.  EMBA Test Cases
Test Case Objective Description Passing Criteria
EMBA.1 Check if extended multiblock lock is asserted only after the assertion of sync header lock.
The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_rx_emb_lock
  • j204c_rx_int
  • The j204c_rx_emb_lock is asserted after assertion of j204c_rx_sh_lock.
  • The j204c_rx_int signal should stay low if there is no error.
EMBA.2 Check if extended multiblock lock status is stable (after extended multiblock lock or until elastic buffer is released) along with no invalid multiblock. The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_rx_emb_lock
  • j204c_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_emb_lock should remain asserted. 3
  • The j204c_rx_int signal should stay low if there is no error.
EMBA.3 Check the lane alignment. The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_rx_dev_lane_align
  • j204c_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_dev_lane_align is asserted after the assertion of j204c_rx_emb_lock and next LEMC event.
  • The j204c_rx_int signal should stay low if there is no error.
3 The j204c_rx_emb_lock signal should remain asserted after 12 hours.
Level Two Title