1.3.3. ADC Test Results
The following table contains the possible results and their definition.
|PASS||The device under test (DUT) was observed to exhibit conformant behavior.|
|PASS with comments||The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed).|
|FAIL||The DUT was observed to exhibit non-conformant behavior.|
|Warning||The DUT was observed to exhibit behavior that is not recommended.|
|Refer to comments||From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.|
The following table shows the results for test cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, and RXTL.1 with subclass 0, and FCLK_MULP = 2.
|Test No.||L||M||F||E||Lane Rate (Mbps)||ADC Rate (Msps)||Link Clock (MHz)||Result|
The following figure shows the Signal Tap waveform of the ramp pattern data received at output of FPGA receiver transport layer.
The following figure shows the result of the ramp pattern checker at output data of FPGA receiver transport layer.
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