AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

Download
ID 683157
Date 6/22/2020
Public
Document Table of Contents

1.4.1.1. Transmitter Data Link Layer

This test area covers the test cases for tx_rst_n. The JESD204C TX IP will start link operation after tx_rst_n is deasserted. In a typical user application, all run-time registers should be configured when the Avalon® memory-mapped configuration space is out of reset, and before the txlink_clk and txframe_clk are out of reset.

Did you find the information on this page useful?

Characters remaining:

Feedback Message