AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

ID 683157
Date 6/22/2020
Document Table of Contents Transmitter Data Link Layer

This test area covers the test cases for tx_rst_n. The JESD204C TX IP will start link operation after tx_rst_n is deasserted. In a typical user application, all run-time registers should be configured when the Avalon® memory-mapped configuration space is out of reset, and before the txlink_clk and txframe_clk are out of reset.

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