AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.4.1.1. Transmitter Data Link Layer

This test area covers the test cases for tx_rst_n. The JESD204C TX IP will start link operation after tx_rst_n is deasserted. In a typical user application, all run-time registers should be configured when the Avalon® memory-mapped configuration space is out of reset, and before the txlink_clk and txframe_clk are out of reset.

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