AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.3.1.2. Receiver Transport Layer

To check the data integrity of the data stream through the JESD204C receiver IP core and transport layer, the ADC is configured to output the ramp test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204C IP core. The ramp checker in the FPGA fabric checks data integrity for 12 hours.

This figure shows the conceptual test setup for data integrity checking.
Figure 3. Data Integrity Check Using RAMP Pattern Checker
Table 3.  RX Transport Layer Test Cases
Test Case Objective Description Passing Criteria
RXTL.1 Check the transport layer mapping of the data channel using ramp test pattern.

The following signals in <ip_variant_name>_base.v are tapped:

  • j204c_rx_avst_valid
  • j204c_rx_avst_ready
  • j204c_rx_avst_data [(M*S*WIDTH_MULP*N)-1:0] 4 5 6 7
  • rx_patchk_data_error_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The rx_patchk_data_error_int signal indicates a pass or fail for the ramp checker.

  • The j204c_rx_avst_valid is asserted.
  • The j204c_rx_avst_ready is asserted.
  • The rx_patchk_data_error_int should stay low if there is no error.
4 M is the number of converters.
5 S is the number of transmitted samples per converter per frame.
6 WIDTH_MULP is the data width multiplier between the application and transport layers.
7 N is the number of conversion bits per converter.
Level Two Title