126.96.36.199. Receiver Transport Layer
To check the data integrity of the data stream through the JESD204C receiver IP core and transport layer, the ADC is configured to output the ramp test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204C IP core. The ramp checker in the FPGA fabric checks data integrity for 12 hours.
|Test Case||Objective||Description||Passing Criteria|
|RXTL.1||Check the transport layer mapping of the data channel using ramp test pattern.||
The following signals in <ip_variant_name>_base.v are tapped:
The rxframe_clk is used as the sampling clock for the Signal Tap.
The rx_patchk_data_error_int signal indicates a pass or fail for the ramp checker.
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