AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

ID 683157
Date 6/22/2020
Public
Document Table of Contents

1.4.1.1.1. TX_RST

Table 7.  TXRST Test Case
Test Case Objective Description Passing Criteria
TXRST.1 Check if j204c_tx_rst_n is deasserted after the completion of reset sequence.
The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_tx_rst_n
  • j204c_tx_int

The txlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_tx_rst_n is deasserted after power on.
  • The j204c_tx_int signal should stay low if there is no error.
  • AD9081 0x55E[6:4] status register returns 0x6 (Lock State) when the register is read.

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