AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
Public
Document Table of Contents

1.3.1.1.1. Sync Header Alignment

Table 1.  SHA Test Cases
Test Case Objective Description Passing Criteria
SHA.1 Check if Sync Header Lock is asserted after the completion of reset sequence. The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_rx_rst_n
  • j204c_rx_sh_lock
  • j204c_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_sh_lock is asserted after the deassertion of j204c_rx_rst_n.
  • The j204c_rx_int signal should stay low if there is no error.
SHA.2 Check Sync Header Lock status after sync header lock is achieved (or during the EMBA phase) and stable. The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_rx_sh_lock
  • j204c_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_sh_lock should remain asserted. 1
  • The j204c_rx_int signal should stay low if there is no error. 2

1 The j204c_rx_sh_lock signal should remain asserted after 12 hours.
2 The j204c_rx_int signal should not be asserted after 12 hours.

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