1.3.2. JESD204C Intel® FPGA IP and ADC Configurations
The JESD204C Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9081 device configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204C parameters comply with the AD9081 operating conditions.
The hardware checkout testing implements the JESD204C Intel® FPGA IP with the following parameter configurations.
- E = 1
- CF = 0
- FCLK_MULP = 2
- WIDTH_MULP = 4
- Subclass = 0
- SH_CONFIG = CRC-12
- FPGA Management Clock (MHz) = 100
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