Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.5.1.2. Output Configuration

The dedicated output registers for Stratix® series and APEX™ II devices are labeled AO and BO. These positive-edge triggered registers and a multiplexer are used to implement the output path for DDR I/O.
Figure 3. Output DDR I/O Path Configuration for Stratix Series and APEX II DevicesThis figure shows the IOE configuration for DDR outputs in Stratix® series and APEX™ II devices.

On the positive edge of the clock, a high data bit and a low data bit are captured in registers AO and BO. The outputs of these two registers are fed to the input of a 2-to-1 multiplexer, which uses the output register clock as its control signal. A high clock selects the data in register BO, and a low level of the clock selects the data in register AO. This process doubles the data at the I/O pin.

Figure 4. Stratix IOE in DDR Output I/O ConfigurationThis figure shows the IOE configuration for DDR outputs in Stratix® series devices

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