Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.5.2. DDR I/O Timing

Figure 6. DDR I/O Input Timing WaveformThis figure shows the functional timing waveform for the input path. The signal names are the port names used in the ALTDDIO_IN IP core. The datain signal is the input from the pin to the DDR circuitry. The output of register BI is neg_reg_out. The output of latch CI is dataout_1, and the output of register AI is dataout_h. dataout_h and dataout_l feed the logic array and show the conversion of the data from a DDR implementation to positive-edge triggered data.
Figure 7. DDR I/O Output Timing WaveformThis figure shows a functional timing waveform example for the output path with the output enable registered. In this example, the delay switch-on by a half clock cycle is not turned on, so the second output enable register (BOE) is not used. The output enable signal OE is active high and can be driven from a pin or internal logic. The data signals datain_l and datain_h are driven from the logic array to output registers AO and BO. The dataout signal is the output from the DDR circuitry to the pin.

The waveform in the figure reflects the software simulation results. The OE signal is active low in silicon; however, the Quartus® Prime software implements this as active high and automatically adds an inverter before the D input of the OE register AOE. You can change the OE back to active low, if desired.

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