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Ixiasoft
1.1. ALTDDIO Features
1.2. ALTDDIO Common Applications
1.3. ALTDDIO Resource Utilization and Performance
1.4. ALTDDIO Parameter Settings
1.5. ALTDDIO Functional Description
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR
1.7. ALTDDIO_IN IP Core Signals
1.8. ALTDDIO_OUT IP Core Signals
1.9. ALTDDIO_BIDIR IP Core Signals
1.10. Verilog HDL Prototype
1.11. VHDL Component Declaration
1.12. VHDL LIBRARY-USE Declaration
1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives
1.14. Document Revision History
Visible to Intel only — GUID: eis1415324673277
Ixiasoft
1.7. ALTDDIO_IN IP Core Signals
These tables list the input and output ports for the ALTDDIO_IN IP core.
Figure 9. ALTDDIO_IN Ports
Name | Required | Description |
---|---|---|
datain[] | Yes | DDR input data port. Input port WIDTH wide. The datain port should be directly fed from an input pin in the top-level design. |
inclock | Yes | Clock signal to sample the DDR input. The datain port is sampled on each clock edge of the inclock signal. |
inclocken | No | Clock enable for the data clock |
aclr | No | Asynchronous clear input. The aclr and aset ports cannot be connected at the same time. |
aset | No | Asynchronous set input. The aclr and aset ports cannot be connected at the same time. |
sclr | No | Synchronous clear input. The sclr and sset ports cannot be Arria® connected at the same time. The sclr port is available for Arria® GX, Stratix® III, Stratix® II, Stratix® II GX, Stratix® , Stratix® GX, HardCopy II, and HardCopy Stratix® devices only. 1 |
sset | No | Synchronous set input. The sclr and sset ports cannot be connected at the same time. The sset port is available for Arria® GX, Stratix® III, Stratix® II, Stratix® II GX, Stratix® , Stratix® GX, HardCopy II, and HardCopy Stratix® devices only. 1 |
Name | Required | Description |
---|---|---|
dataout_h[] | Yes | Data sampled from datain[] port at the rising edge of the inclock signal. |
dataout_l[] | Yes | Data sampled from datain[] port at the falling edge of the inclock signal. |
1 When designing with Stratix III devices, when sclr is asserted, it synchronously presets both the input path and resynchronization register.
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