1.6.2. Create a Divider
Follow these steps to create a top-level VHDL file:
- In the Quartus® Prime software, with the ex2.qar project open, open the file ex2.vhd.
- On the Project menu, click Add/Remove File in Project. The File Settings page displays.
- In the File Settings window, click (...) after File name and browse for ex2.vhd in the project folder.
- Select ex2.vhd and click Add.
- Click OK.
The top-level file is added to the project. You have now created the complete design file.
This design implements the divider with the functionality of the ALTDDIO_IN and ALTDDIO_OUT IP cores implemented in a single IP core, ALTDDIO_BIDIR. The bidirectional pins DDR_BIDIR8[7..0] receive data at double the clock rate. The DDRBIDIR8_OUT_H[7..0] signals are the numerator and the DDRBIDIR8_OUT_L[7..0] signals are the denominator. These two sets of signals are passed to the lpm_divide IP core where the quotient and remainder are calculated. The divider calculates the quotient and remainder with a one-stage pipeline. The quotient and remainder are then fed via signals quotient[7..0] and remain[7..0] back to the ALTDDIO_BIDIR megafunction. The ALTDDIO_BIDIR megafunction then drives the data out through pins DDR_BIDIR8[7..0] at double the data rate.
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