Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.5.1.1. Input Configuration

When the IOE is configured as an input pin, input registers AI and BI and latch CI implement the input path for DDR I/O.
Figure 1. Input DDR I/O Path Configuration for a Stratix Series or APEX II DeviceThis figure shows an IOE configured for DDR inputs for a Stratix® series or APEX™ II device.
Note: On the falling edge of the clock, the negative-edge triggered register BI acquires the first data bit. On the corresponding rising edge of the clock, the positive-edge triggered register AI acquires the second data bit. For a successful data transfer to the logic array, the latch CI synchronizes the data from register BI to the positive edge of the clock.
Figure 2. Stratix II IOE in DDR Input I/O ConfigurationThis figure shows an IOE configured for DDR inputs for a Stratix® or Stratix®  II device.

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