188.8.131.52. Create the LPM_DIVIDE IP core
- On the Tools menu, select IP Catalog.
- In the IP catalog, double-click LPM_DIVIDE.
- Specify the IP variation file name and click OK.
- In the parameter editor pages, select or verify the configuration settings shown in the following table. Click Next to advance from one page to the next.
Page Parameter Value 2a Which megafunction would you like to customize In the Arithmetic folder, select LPM_DIVIDE Which device family will you be using? Stratix Which type of output file do you want to create? VHDL What name do you want for the output file? lp_div Return to this page for another create operation Turned off 3 Currently selected device family Stratix IV Match project/default Turned on How wide should the ‘numerator’ input bus be? 8 How wide should the ‘denominator’ input bus be? 8 Numerator Representation Select Unsigned Denominator Representation Select Unsigned 4 Do you want to pipeline the function? Select Yes, I want an output latency of 1 clock cycle Create an Asynchronous Clear input Turned off Create a Clock Enable input Turned off Which do you wish to optimize? Select Default Optimization Always return a positive remainder? Select Yes 5 Generate netlist Turned off 6 Variation file Turned on Quartus II IP file Turned on Quartus II symbol file (.bsf) Turned off Instantiation template file Turned on Verilog HDL black box file (_bb.v) Turned on AHDL Include file (.inc) Turned off VHDL component declaration file (.cmp) Turned on PinPlanner ports file (.PPF) Turned on
- Click Finish.
The lpm_divide IP core variation is now built.
Did you find the information on this page useful?