Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.6.4. Functional Results—Simulate the Divider Design in the ModelSim* - Intel FPGA Edition Software

Simulate the design in the ModelSim* - Intel FPGA Edition software to generate a waveform display of the device behavior.

To set up the ModelSim* - Intel FPGA Edition software, follow these steps:

  1. Unzip the ALTDDIO_ex2_msim.zip file to any working directory on your PC.
  2. Browse to the folder in which you unzipped the files and open the ALTDDIO_ex2.do file in a text editor.
  3. In line 1 of the ALTDDIO_ex2.do file, replace <insert_directory_path_here> with the directory path of the appropriate library files. For example, C:/altera/71/modelsim_ae/altera/verilog/stratix
  4. On the File menu, click Save.
  5. Start ModelSim* - Intel FPGA Edition .
  6. On the File menu, click Change Directory.
  7. Select the folder in which you unzipped the files. Click OK.
  8. On the Tools menu, click Execute Macro.
  9. Select the ALTDDIO_ex2.do file and click Open. This is a script file for ModelSim that automates all the necessary settings for the simulation.
  10. Verify the results by looking at the Waveform Viewer window.

    You can rearrange signals, remove redundant signals, and change the radix by modifying the script in the ALTDDIO_ex2.do file.

Figure 8. ModelSim Simulation ResultsThis figure shows the expected simulation results in ModelSim* - Intel FPGA Edition software.

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