Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.4. ALTDDIO Parameter Settings

These tables list the parameter settings for the ALTDDIO IP cores.
Table 1.  ALTDDIO_IN Parameter SettingsThis table lists the parameter settings for the ALTDDIO_IN IP core.
Parameter Description
Currently selected device family Specify the Altera device family you are using.
Width: (bits) Specify the width of the data buses.
Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr). Select Use ‘aset’ port for asynchronous preset (aset).

If you are not using any of the asynchronous clear options, select Not used and specify whether registers should power up high or low by turning on/off Registers power up high.

Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr). Select Use ‘sset’ port for synchronous preset (sset). If you are not using any of the synchronous clear options, select Not used.

The synchronous reset option is available for Arria®  GX, Stratix®  III, Stratix®  II, Stratix®  II GX, Stratix® , Stratix®  GX, HardCopy II, and HardCopy Stratix® devices only.

Use ‘inclocken’ port Turn on this option to add a clock enable port that controls when data input is clocked in. This signal prevents data from being passed through.
Invert input clock When enabled, the first bit of data is captured on the rising edge of the input clock. If not enabled, the first bit of data is captured on the falling edge of the input clock.
Table 2.  ALTDDIO_OUT Parameter SettingsThis table lists the parameter settings for the ALTDDIO_OUT IP core.
Parameter Description
Currently selected device family Specify the Altera device family you are using.
Width: (bits) Specify the width of the data buses.
Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr). Select Use ‘aset’ port for asynchronous preset (aset).

If you are not using any of the asynchronous clear options, select Not used and specify whether registers should power up high or low by turning on/off Registers power up high.

Use ‘outclocken’ port Turn on this option to add a clock enable port to control when data output is clocked in. This signal prevents data from being passed through.
Invert ‘dataout’ output Turn on this option to invert the dataout[] output port. This option is available for Cyclone®  III and Cyclone®  II devices only.
Use output enable port Turn on this option to create an output enable input port (oe) to control when the data is set out to the dataout port.
Use ‘oe_out’ port to connect to tri-state output buffer(s) Turn on this option to create an output enable port for the bidirectional padio port. This port is available for Stratix®  III and Cyclone®  III devices only.
Register ‘oe’ port Turn on this option tp register the output-enable (oe) input port.
Delay switch-on by half a clock cycle Turn on this option to use an additional oe register. When the additional oe register is used, the output pin is held at high impedance for an extra half clock cycle after the oe port goes high.
Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr). Select Use ‘sset’ port for synchronous preset (sset). If you are not using any of the synchronous clear options, select Not used.

The synchronous reset option is available for Arria®  GX, Stratix®  III, Stratix®  II, Stratix®  II GX, Stratix® , Stratix®  GX, HardCopy II, and HardCopy Stratix® devices only.

Table 3.  ALTDDIO_BIDIR Parameter SettingsThis table lists the parameter settings for the ALTDDIO_BIDIR IP core. The ALTDDIO_BIDIR IP core combines the ALTDDIO_IN and ALTDDIO_OUT IP core functionality into a single IP core, which instantiates bidirectional DDR ports.
Parameter Description
Currently selected device family Specify the Altera device family you are using.
Width: (bits) Specify the width of the data buses.
Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr). Select Use ‘aset’ port for asynchronous preset (aset).

If you are not using any of the asynchronous clear options, select Not used and specify whether registers should power up high or low by turning on/off Registers power up high.

Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr). Select Use ‘sset’ port for synchronous preset (sset). If you are not using any of the synchronous clear options, select Not used.

The synchronous reset option is available for Arria®  GX, Stratix®  III, Stratix®  II, Stratix®  II GX, Stratix® , Stratix®  GX, HardCopy II, and HardCopy Stratix® devices only.

Invert ‘padio’ port The ‘padio’ port is inverted whenever driven as an output. This option is available for Cyclone®  III and Cyclone®  II devices only.
Use ‘inclocken’ and ‘outclocken’ ports Turn on this option to add a clock enable port to control when data input and output are clocked in. This signal prevents data from being passed through.
Use output enable port Turn on this option to create an output enable input port (oe) to control when the data is set out to the dataout port.
Use oe_out port to connect to tri-state output buffer(s) Output enable for the bidirectional padio port. This port is available for Stratix®  III and Cyclone®  III devices only.
Register ‘oe’ port Turn on this option to register the output-enable (oe) input port.
Delay switch-on by a half clock cycle Turn on this option to use an additional oe register. When the additional oe register is used, the output pin is held at high impedance for an extra half clock cycle after the oe port goes high.
Use ‘combout’ port Use the optional data port combout. The combout port sends data to the core, bypassing the DDR I/O input registers. For bidirectional operation, you must enable the dataout_h and dataout_l ports, the combout port, or both.
Use ‘dqsundelayedout’ port Creates undelayed output from the DQS pins. If you use the ALTDDIO_BIDIR IP core for your DQS signal in an external memory interface, you route the undelayed DQS signal to the LE, in Stratix®  II and Stratix® devices. This option is available in Stratix® , Stratix®  GX, and HardCopy  Stratix® devices only.
Use ‘dataout_h’ and ‘dataout_l’ ports Enables the dataout_h and dataout_l ports.
Implement input registers in LEs Implements the input path in logic elements. This option is available only if the dataout_h and dataout_l ports are enabled.

Did you find the information on this page useful?

Characters remaining:

Feedback Message