Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.10. Verilog HDL Prototype

The Verilog HDL prototype is located in the < Quartus® Prime installation directory>\eda\synthesis\altera_mf.v

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