22.214.171.124. Create the ALTDDIO_BIDIR IP Core
- Unzip the ALTDDIO_DesignExample_ex2.zip file to any working directory on your PC.
- In the Quartus® Prime software, open the ex2.qar project .
- In the IP catalog, double-click ALTDDIO_BIDIR.
- Specify the IP variation file name and click OK.
- In the parameter editor pages, select or verify the configuration settings shown in the following table. Click Next to advance from one page to the next.
Parameter Editor Page Parameter Value 2a Which megafunction would you like to customize In the I/O folder, select ALTDDIO_BIDIR Which device family will you be using? Stratix® Which type of output file do you want to create? VHDL What name do you want for the output file? alt_bid Return to this page for another create operation Turned off 3 Currently selected device family Stratix® IV Match project/default Turned on Width: (bits) 8 Use ‘aclr’ port Turned off Use ‘aset’ port Turned off Not used Turned on Registers power up high Turned off Use ‘sclr’ port Turned off Use ‘sset’ port Turned off Not used Turned on Invert ‘padio’ port Turned off 4 Use ‘inclocken’ and ‘outclocken’ ports Turned off Use output enable port Turned on Use ‘oe_out’ port to connect to tri-state output buffer(s) Turned off Register ‘oe’ port Turned off Delay switch-on by half a clock cycle Turned off Use ‘combout’ port Turned off Use ‘dqsundelayedout’ port Turned off Use ‘dataout_h’ and ‘dataout_l” ports Turned on Implement input registers in LEs Turned off 5 Generate netlist Turned off 6 Variation file Turned on Quartus® Prime IP file Turned on Quartus® Prime symbol file (.bsf) Turned off Instantiation template file Turned on Verilog HDL black box file (_bb.v) Turned on AHDL Include file (.inc) Turned off VHDL component declaration file (.cmp) Turned on PinPlanner ports file (.PPF) Turned on
- Click Finish.
The ALTDDIO_BIDIR IP core variation is now built.
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