Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 9/26/2022
Public
Document Table of Contents

3.1. Using Interface Planner

After design synthesis, you can use Interface Planner to help you to rapidly define a legal device floorplan.

Interface Planner displays your project's logical hierarchy, post-synthesis design elements, and Fitter-created design elements, alongside a view of target device locations. The GUI supports a variety of methods for placing design elements in the floorplan. As you place elements in the floorplan, the Fitter verifies legality in real time to ensure accurate correlation with the final implementation.

Intel® FPGAs contain core and periphery device locations. The device core locations are adaptive look-up tables (ALUTs), core flip-flops, RAMs, and digital signal processors (DSPs). Device periphery locations include I/O elements, phase-locked loops (PLLs), clock buffers, and hard processor systems (HPS).

Figure 6.  Interface Planner Streamlines Legal Placement

Intel® FPGAs contain many silicon features in the device periphery, such as hard PCI Express® IP cores, high speed transceivers, hard memory interface circuitry, and embedded processors. Interactions among these periphery elements can be complex. Interface Planner simplifies this complexity and allows you to quickly visualize and place I/O interface and periphery elements, such as:

  • I/O elements
  • LVDS interfaces
  • PLLs
  • Clocks
  • Hard interface IP Cores
  • High-Speed Transceivers
  • Hard Memory Interface IP Cores
  • Embedded Processors

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