18.104.22.168. Overriding Default I/O Pin Analysis
You can override the default I/O analysis of pins to accommodate I/O rule exceptions, such as for analyzing VREF or inactive pins.
Each device contains VREF pins, each supporting one or more I/O pins. A VREF pin and its I/O pins comprise a VREF bank. The VREF pins are typically assigned inputs with VREF I/O standards, such as HSTL- and SSTL-type I/O standards. Conversely, VREF outputs do not require the VREF pin. When a voltage-referenced input is present in a VREF bank, only a certain number of outputs can be present in that VREF bank. I/O assignment analysis treats bidirectional signals controlled by different output enables as independent output enables.
To assign the Output Enable Group option to bidirectional signals to analyze the signals as a single output enable group, follow these steps:
- To access this assignment in the Pin Planner, right-click the All pins list and click Customize Columns.
- Under Available columns, add Output Enable Group to Show these columns in this order. The column appears in the All Pins list.
- Enter the same integer value for the Output Enable Group assignment for all sets of signals that are driving in the same direction.
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