Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 9/26/2022
Document Table of Contents

3.2.1. Tile Interface Planner Terminology

Tile Interface Planner refers to the following terminology:
Table 16.  Tile Interface Planner Terminology
Term Description
Dynamic Reconfiguration Intel FPGA IP technology that allows you to modify some features of a supported multi-rate Intel® FPGA IP interface in real time while the FPGA remains in operation. For example, you can dynamically reconfigure the settings in the F-tile CPRI PHY Multi-Rate Intel® FPGA IP to run your design at different data rates and features for different IP "profiles."
Floorplan The layout of physical resources on the device. Creating a design floorplan, or floorplanning, is the process of mapping the logical design hierarchy to physical regions in the device. Tile Interface Planner is a tile IP floorplanning tool.
IP building block

Intel® FPGA IP cores are comprised of building blocks that combine to provide all functionality of the IP. The Design Tree view in Tile Interface Planner displays each IP's building blocks. Building blocks can be movable, fixed, or always movable types.

  • Movable building blocks—building blocks are initially movable. Movable building blocks can be re-placed by the legality engine in potentially one of several legal locations to accommodate other building blocks. You can convert a movable building block to fixed by specifying a fixed placement location. The legality engine cannot change the placement of fixed building blocks. Movable building block placements appear in italic text in the Design Tree view. Movable building blocks have a dithered fill in Chip View.
  • Fixed building blocks—building blocks that you place in a fixed, legal location that the legality engine cannot change. You can convert a movable building block to fixed, and a fixed building block to movable. Fixed building block placements appear in plain text in the Design Tree view. Fixed building blocks have a solid fill In the Chip View.
  • Always movable building blocks—building blocks that are always movable by the legality engine and cannot be fixed. These building blocks must remain movable to prevent inadvertent conflicting constraints. Always movable building blocks appear in gray italic text in the Design Tree view.
Intel® Quartus® Prime Settings File (.qsf) Intel® Quartus® Prime software file that preserves project settings and assignments, including the placement of fixed IP building blocks and fixed tile assignments that you specify in Tile Interface Planner.
JSON file Intel® Quartus® Prime software internal file that preserves the most recent placement from the Logic Generation stage of the Compiler. You can load this placement when you click Update Assignments if you want the starting point for planning to include the last Logic Generation assignments.
Legal location Tile Interface Planner legality engine identifies the legal locations in the tile floorplan for placement of the IP or building block that you select in the Design Tree.
Legality engine Tile Interface Planner function that generates valid legal locations for tile placement, and places movable and always movable building blocks in the tile plan.
Placed design element IP or building block that you or the legality engine has assigned to a fixed or movable legal location.

Support-Logic Generation stage

A Compiler stage, preceding Analysis & Synthesis, that includes the Design Analysis and Logic Generation sub-stages. This stage is only present when targeting F-tile.
  • Design Analysis stage—A Compiler stage, preceding Analysis & Synthesis, that elaborates the design RTL to extract design information about component IP targeting F-tile. You must run this stage before running Tile Interface Planner. This stage is not present for other FPGA device families or for designs without required IP.
  • Logic Generation stage—A Compiler stage, following Design Analysis, that uses your Tile Interface Plan to generate logic for synthesis and implementation of your tile configuration plan. You must run Logic Generation after Design Analysis before you can synthesize your tile plan.
Tile plan One or more fixed placements that you define and save in Tile Interface Planner using the (.qsf).
Unplaced design element IP or building blocks that are unassigned to a fixed or movable legal location.

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