22.214.171.124. Specify Instance-Specific Constraints in Assignment Editor 126.96.36.199. Specifying Multi-Dimensional Bus Constraints 188.8.131.52. Specify I/O Constraints in Pin Planner 184.108.40.206. Plan Interface Constraints in Interface Planner and Tile Interface Planner 220.127.116.11. Adjust Constraints with the Chip Planner 18.104.22.168. Constraining Designs with the Design Partition Planner
22.214.171.124. Specify I/O Constraints in Pin Planner
Intel® Quartus® Prime Pin Planner allows you to assign design elements to I/O pins. You can also plan and assign IP interface or user nodes not yet defined in the design.
Figure 2. Pin Planner GUI
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